The technical field relates generally to computer architecture and more particularly, but not by way of limitation, to a method and apparatus for allowing repeatable system behavior in an integrated circuit with multiple clock domains by ensuring that a reset takes effect at the same time with respect to each clock.
In the field of integrated circuit (IC) chip design, it is necessary to test the chips to identify any bugs that may exist. However, debugging becomes more difficult as the level of system complexity increases. The debugging process is expensive in terms of time spent identifying bugs and the equipment that must be used in this process. In complex systems, it is impractical to monitor every signal from a system under test. Instead, when an error is detected during a test, the test is re-executed on an instrumented prototype to isolate the cause of the failure. To reproduce the test failure on the instrumented prototype, it is essential that the test program execute with the test hardware in exactly the same state that existed when it executed on the original system on which it failed. That is, the system must be repeatable. If the system is not repeatable, then the debugging process takes substantially longer because the same error or bug may not appear in a subsequent test.
One source of non-repeatability has been traced to the relationship between different clocks within the system. A system or an integrated circuit (IC) may use multiple clock domains. In a system with multiple clock domains, a repeatability problem occurs when the system receives an asynchronous event, such as a system reset signal or an interrupt. The problem results because the asynchronous event may take effect at different times for each clock domain. A system may, for example, have a system clock, which is divided into lower frequency clocks, using a clock divider or other means of providing multiple clocks. The system clock and the lower frequency clocks may be distributed to the integrated circuits (IC) in the system. It is impractical due to space constraints to use a single clock divider and to run each clock to every chip in the system. So, existing systems route the system clock throughout the system and then use multiple clock dividers or other means to provide various clocks to chips as needed.
Also throughout existing systems, every IC also has a reset input that triggers when the system must be reset. The reset on each chip actually occurs on the high edge of some clock used by the chip. That is, the reset may be sent to the entire system asynchronously, so in each chip it waits for the next clock cycle to reset. The same situation is true of any asynchronous event that enters the system, such as interrupts and external signals.
Several problems exist due to the use of multiple clock dividers and multiple clock domains. By using multiple clock dividers, each chip""s clock may be out of synchronization with other chips"" clocks, even those at the same frequency. A system may have a system clock with frequency F. That system clock is then divided into various lower-frequency clocks throughout the system, e.g. F/2, F/4. In existing methods, the system clock is routed throughout the system to each chip. Each chip then divides the system clock to create lower frequency clocks for use in the particular chip. The problem with these systems is that each chip divides the system clock at an arbitrary point in the clock cycle. Each time these systems start, the lower frequency clocks may be in a different state. For example, two chips may divide a the system clock to produce a frequency of F/2, yet even if those F/2 clocks are synchronous, they may still be out of phase with respect to each other. The problem becomes even more pronounced in more complicated systems involving multiple chips, each of which may produce multiple clocks. When the clocks throughout the system are out of phase with respect to each other, it becomes difficult to control the state of the system and to create repeatability.
One problem in particular relates to the handling of asynchronous events, such as a reset function. In a system with multiple clock domains, the asynchronous event may be seen at different times in different domains. Even in a system having a single clock divider and multiple clock domains, a problem still exists with respect to these events. Because the event enters the system asynchronously, different clock domains realize the event at different times. Also, these times may be different every time the system is tested, depending upon the clock states during the test.
FIG. 1 illustrates a problem with controlling the clock state, using a system reset function as an example of an asynchronous event. FIG. 1 shows two separate clock cycles for a fast clock and a slow clock in which the clocks are synchronous and have corresponding rising edges. The fast clock has a frequency equal to twice that of the slow clock. In the example shown in FIG. 1, the reset occurs when the slow clock is high and the fast clock is low. The reset is not sent to the system until the occurrence of a rising clock edge. In the example shown, the reset is realized on part of the chip sooner than it is realized on other parts of the chip. That is, the reset is realized on the rising clock edge of the fast clock first, for those parts of the chip within the fast clock""s domain. In the example of FIG. 1, those parts of the chip within the slow clock""s domain do not realize the reset until some time later when it has a rising edge. The difference in clock speeds prevents the reset from being seen throughout the entire chip at the same time. FIG. 1 is a simplified version of a system having only two clocks shown. Obviously, the problem becomes substantially more complex in systems that use multiple clock domains.
The problem with the delay between clock domains comes in the area of debugging the system. In order to debug the system, it is desirable to recreate the exact situation that caused the error. To do that, it is necessary to insure that the system is in exactly the same state that it was when the error occurred. To insure that, the asynchronous event must be sent throughout the entire chip at the same time. What is needed is a common reference for all system clocks without the difficulty caused by running every clock throughout the system. In particular, with respect to the handling of asynchronous events, what is needed is a method and an apparatus for allowing the event to take effect at a single instance throughout an IC or a system having multiple clock domains.
A method and apparatus are disclosed for allowing a system having multiple clock domains to be put into a known state to ensure repeatability during debugging tests. A global framing clock is created having a frequency equal to the lowest common denominator of all clocks in the system or to some divisor thereof. At this frequency, the global framing clock ensures that it will have a rising edge at the same time that other clocks in the system have rising edges. The system clock and the global framing clock are run throughout the system to integrated circuits.
The global framing clock is used to control a system function, such as a reset or an interrupt function. When the system receives an asynchronous event, the global framing clock ensures that the event is not distributed to the system until the occurrence of a rising edge of the global framing clock. This ensures that the event will also be seen on a rising edge of every other system clock, which makes the event appear at the same time throughout the system. By ensuring that an asynchronous function, such as a reset function, appears at the same time throughout the system, the system becomes repeatable. That is, the clock states will be the same every time an asynchronous event is released to the system.